Spin me right round rotational symmetry for FPGA-specific AES
- The effort in reducing the area of AES implementations has largely been focused on application-specific integrated circuits (ASICs) in which a tower field construction leads to a small design of the AES S-box. In contrast, a naive implementation of the AES S-box has been the status-quo on field-programmable gate arrays (FPGAs). A similar discrepancy holds for masking schemes—a well-known side-channel analysis countermeasure—which are commonly optimized to achieve minimal area in ASICs. In this paper, we demonstrate a representation of the AES S-box exploiting rotational symmetry which leads to a 50% reduction in the area footprint on FPGA devices. We present new AES implementations which improve on the state-of-the-art and explore various trade-offs between area and latency. For instance, at the cost of increasing 4.5 times the latency, one of our design variants requires 25% less look-up tables (LUTs) than the smallest known AES on Xilinx FPGAs by Sasdrich and Güneysu at ASAP 2016. We further explore the protection of such implementations against side-channel attacks. We introduce a generic methodology for masking any \(\it n\)-bit Boolean functions of degree \(\it t\) with protection order \(\it d\). The methodology is exact for first-order and heuristic for higher orders. Its application to our new construction of the AES S-box allows us to improve previous results and introduce the smallest first-order masked AES implementation on Xilinx FPGAs, to date.
Author: | Felix WegenerGND, Lauren De MeyerGND, Amir MoradiORCiDGND |
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URN: | urn:nbn:de:hbz:294-89248 |
DOI: | https://doi.org/10.1007/s00145-019-09342-y |
Parent Title (English): | Journal of cryptology |
Subtitle (English): | extended version |
Publisher: | Springer Nature |
Place of publication: | New York |
Document Type: | Article |
Language: | English |
Date of Publication (online): | 2022/05/12 |
Date of first Publication: | 2020/01/22 |
Publishing Institution: | Ruhr-Universität Bochum, Universitätsbibliothek |
Tag: | AES; DPA; FPGA; Rotational symmetry; SCA; Threshold implementations; d+1 Masking |
Volume: | 33 |
First Page: | 1114 |
Last Page: | 1155 |
Note: | Dieser Beitrag ist auf Grund des DEAL-Springer-Vertrages frei zugänglich. |
Institutes/Facilities: | Horst Görtz Institut für IT-Sicherheit |
Dewey Decimal Classification: | Allgemeines, Informatik, Informationswissenschaft / Informatik |
open_access (DINI-Set): | open_access |
Licence (English): | Creative Commons - CC BY 4.0 - Attribution 4.0 International |